摘 要

非制冷红外热探测器不论是在军事上，还是在民用上都具有广泛应用前景，纳结构热探测器阵列的CMOS读出电路是非制冷红外探测器的核心部件。长期以来，西方的各发达国家对红外热成像方面的开发和研制工作都非常重视；而我国在红外焦平面CMOS读出电路的开发和研制测试方面起步较晚，涉足该领域才20多年。由于非制冷红外焦平面探测器在军事方面具有重大意义，所以我国迫切需要拥有自己在这方面的知识产权。而探测器阵列的读出电路在非制冷红外焦平面成像系统中扮演着不可或缺的角色。

纳结构热探测器阵列CMOS读出电路设计的主要难点在于处理红外探测器输出的电信号是uA级的电流信号难度高，电路结构设计复杂，工作量较为繁复。在设计读出电路时，需要把uA级的电流信号放大变成电压信号。同时，还要尽可能的抑制电路中的各种噪声信号防止噪声信号对探测器信号。因此，需要设计电容跨导运放大器电路结构和双采样电路结构，以及读出电路时序控制电路。

本文的研究内容主要如下：

（1）在研究纳结构热探测器阵列工作原理及其性能的基础上，对纳结构热探测器CMOS读出电路性能参数进行探究分析，从噪声来源方面对CMOS读出电路中存在的噪声进行分析，并提出抑制方法，通过四种读出电路结构的优缺点比较，最终选择一种最适当的读出电路结构；

（2）使用cadence IC软件设计了二级运算放大器以及电压信号采样保持电路，并使用设计的运算放大器完成电容跨导运算放大器CTIA电路的设计，再对设计的运算放大器和CTIA电路进行仿真分析；

（3）使用cadence IC软件设计了折叠式共源共栅运算放大器，并使用设计的折叠式共源共栅运算放大器完成相关双采样CDS电路的设计，再使用spectra仿真器对设计的折叠式共源共栅运算放大器和CDS电路进行仿真分析；

（4）使用cadence IC软件完成了单元热探测器CMOS读出电路设计，在单元读出电路的基础上完成10线元CMOS读出电路设计，再使用spectra仿真器对单元热探测器CMOS读出电路仿真分析；实验结果分析表明，设计的CMOS读出电路功耗小于20mW、输出噪声小于1mV、积分时间为20uS及每秒输出像元数为10K等，设计的电路达到了性能要求；

（5）在完成纳结构热探测器CMOS读出电路的基础上，完成了CMOS读出电路时序控制电路的设计与仿真分析。通过设计纳结构热探测器阵列的CMOS读出电路，熟悉纳结构探测器工作原理，为以后研究与红外技术相关的非制冷焦平面热探测器阵列奠定基础。

关键词：纳结构热探测器阵列；CMOS读出电路；电容跨导积分放大器；采样保持；相关双采样

Abstract

The CMOS readout circuit of the nano-structure thermal detector array is the core component of the uncooled infrared detector, and it has wide application prospect both in the military and in the civil use. For a long time, the developed countries in the West have made great attention to the exploitation and development of infrared thermal imaging. And China in the infrared focal plane CMOS readout circuit development and development testing started late, involved in the field only 20 years. As the non-refrigerated infrared focal plane in the military is of great significance, so our urgent need to have their own intellectual property in this area. And the detector circuit of the detector array plays an indispensable role in the uncooled infrared focal plane imaging system.

The main difficulty in the design of the array CMOS detector circuit is that the electrical signal output by the infrared detector is the uA level current signal, the circuit structure design is complicated and the workload is complicated. In the design of the read circuit, the need to uA level of the current signal amplification into a voltage signal. At the same time, but also as much as possible to suppress the various noise signals in the circuit to prevent the noise signal on the detector signal. Therefore, it is necessary to design a capacitor trans-conductor amplifier circuit structure and a dual sampling circuit structure, as well as a readout circuit timing control circuit.

The main contents of this paper are as follows:

(1) Based on the study of the working principle and performance of the nanostructure thermal detector array, the performance parameters of the CMOS readout circuit of the nanostructure thermal detector are analyzed and analyzed, and the noise in the CMOS readout circuit is studied from the noise source Analysis and proposed suppression method, through the four readout circuit structure of the advantages and disadvantages of comparison, the final choice of a most appropriate readout circuit structure;

(2) The use of cadence IC software to design a two-stage operational amplifier and voltage signal sampling and hold circuit, and the use of operational amplifier to complete the design of the capacitor transconductance amplifier (CTIA) circuit, followed by the design of the operational amplifier and CTIA circuit Simulation analysis;

(3) Design a folded cascode op amp using the cadence IC software and use the designed foldable cascode op amp to complete the design of the associated dual sampling (CDS) circuit, and then use the spectra simulator to fold the design Type cascode operational amplifier and CDS circuit for simulation analysis;

(4) Using the cadence IC software to complete the unit thermal detector CMOS readout circuit design, and in the unit readout circuit based on the completion of 10-wire CMOS readout circuit design, and then use the noise simulator on the unit thermal detector CMOS readout circuit simulation The experimental results show that the designed CMOS readout circuit consumes less than 20mW, the output noise is less than 1mV, the integration time is 20uS and the output pixel number is 10K per second. The designed circuit achieves the performance requirement.

(5) Based on the completion of the nano-structure thermal detector CMOS readout circuit, the design and simulation analysis of the CMOS readout circuit timing control circuit is completed. By designing the CMOS readout circuit of the nanostructure thermal detector array, we are familiar with the working principle of the nanostructure detector and lay the foundation for the future study of the array of uncooled focal plane thermal detectors related to infrared technology.

Keywords: CMOS readout circuit; the nanostructure thermal detector array; CTIA; Sampling and holding; CDS

目 录

摘 要 I

Abstract II

第1章 绪论 1

1.1 课题研究的目的及意义 1

1.2 国内外发展和研究现状 2

1.3 本文主要研究内容 3

第2章 纳结构热探测器读出电路研究分析 4

2.1 纳结构热探测器工作原理及性能分析 4

2.2 CMOS读出电路性能参数分析 6

2.3 CMOS读出电路噪声分析及抑制 7

2.4几种常见CMOS读出电路结构分析 9

2.5 本章小结 12

第3章 CTIA型纳结构热探测器读出电路设计与仿真分析 13

3.1 读出电路模块电路设计与仿真分析 13

3.1.1 CTIA电路运算放大器设计 14

3.1.2 CTIA电路运算放大器仿真分析 19

3.1.3 CTIA电路设计与仿真分析 22

3.1.4 CDS电路运算放大器设计 25

3.1.5 CDS电路运算放大器仿真分析 27

3.1.6 CDS电路设计与仿真分析 29

3.2 单元读出电路总体性能仿真分析 31